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| Semiconductor MS81V06160 (401,408-word x 16-bit) FIFO memory This version: Sep. 2000 Preliminary GENERAL DESCRIPTION The MS81V06160 is a 6Mb FIFO (First-In First-Out) memory designed for 401,408-words x 16-bit high-speed asynchronous read/write operation. The MS81V06160 is best suited for a field memory for digital TVs or LCD panels which require high-speed, large memory , and is not designed for high end use in professional graphics systems, which require long term picture storage and data storage. The MS81V06160 is provided with independent control clocks to support asynchronous read and write operations. Different clock rates are also supported, which allow alternate data rates between write and read data streams. The first data read operation can be performed after 1600 ns + 4 cycles from read reset and the first data write operation is enabled after 1600 ns + 4 cycles from write reset. Thereafter, the high-speed read/write operation is possible every cycle time. Additionally, a write mask function by IE pin and a read-data skipping function by OE pin implement image data processing easily. The MS81V06160 provides high speed FIFO (First-in First-out) operation without external refreshing: MS81V06160 refreshes its DRAM storage cells automatically, so that it appears fully static to the users. Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic. The MS81V06160's function is simple, and similar to a digital delay device whose delay-bit- length is easily set by reset timing. The delay length and the number of read delay clocks between write and read, is determined by externally controlled write and read reset timings. The MS81V06160 uses a thin and small 70-pin plastic TSOP. 1/18 Semiconductor MS81V06160 FEATURES * * * * * * * * * 401,408 words x 16 bits Fast FIFO (First-In First-Out) operation: 12 ns cycle time Self refresh (No refresh control is required) High speed asynchronous serial access Read/Write Cycle Time 12 ns/15 ns Access Time 9 ns/12 ns Variable length delay bit (600 to 401,408) Write mask function (Output enable control) Cascading capability Single power supply: 3.3 V 10% Package: 70-pin plastic TSOP TYPE II (TSOP II 70-P-400-0.5-K) (Product name: MS81V06160-xxTA) xx indicates speed rank. Parameter Access Time Read/Write Cycle Time Operation current Standby current Symbol tAC tSWC tSRC Icc1 Icc2 MS81V06160-TA -12 9 ns 12 ns 210 mA 6 mA -15 12 ns 15 ns 170 mA 6 mA 2/18 Semiconductor MS81V06160 PIN CONFIGURATION (TOP VIEW) VCC NC NC NC VSS DI0 DI1 DI2 DI3 VSS DO0 DO1 VCC DO2 DO3 VSS VSS VCC VCC DO4 DO5 VCC DO6 DO7 VSS DI4 DI5 DI6 DI7 VSS OE RE RSTR SRCK VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 VSS NC NC NC VCC DI15 DI14 DI13 DI12 VSS DO15 DO14 VCC DO13 DO12 VSS VSS VCC VCC DO11 DO10 VCC DO9 DO8 VSS DI11 DI10 DI9 DI8 VCC IE WE RSTW SWCK VSS 70-pin Plastic TSOP SWCK SRCK WE RE IE OE RSTW RSTR DI0-15 DO0-15 VSS VCC NC Serial Write Clock Serial Read Clock Write Enable Read Enable Input Enable Output Enable Reset Write Reset Read Data Input Data Output Ground (0 V) Power Supply (3.3 V) No Connection Note: The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 3/18 Semiconductor MS81V06160 BLOCK DIAGRAM DO (X16) OE RE RSTR SRCK Data-output Buffer Serial Read Controller Read Data Register (X16) 401,408 x 16 Memory Array X Decoder Read/Write Refresh Timing Generater (X16) Write Data Register Refresh Counter Data-input Buffer Serial Write Controller DI (X16) IE WE RSTW SWCK 4/18 Semiconductor MS81V06160 PIN DESCRIPTION Data Inputs: (DI0-15) These pins are used for serial data inputs. Write Reset: RSTW The first positive transition of SWCK after RSTW becomes high resets the write address pointers to zero. RSTW setup and hold times are referenced to the rising edge of SWCK. Write Enable: WE WE is used for data write enable/disable control. WE high level enables the input, and WE low level disables the input and holds the internal write address pointer. There are no WE disable time (low) and WE enable time (high) restrictions, because the MS8106160 is in fully static operation as long as the power is on. Note that WE setup and hold times are referenced to the rising edge of SWCK. The latency for the write operation control by WE is 2. After write reset, WE must remain low for more than 1600 ns (tFWD). After write reset, the write operation at address 0 is started after a time tWL form the cycle in which WE is brought high. After write reset, WE should be remained high for 2 cycles after driving WE high first. Input Enable: IE IE is used to enable/disable writing into memory. IE high level enables writing. The internal write address pointer is always incremented by cycling SWCK regardless of the IE level. Note that IE setup and hold times are referenced to the rising edge of SWCK. The latency for the write operation control by IE is 2. Data Out: (DO0-15) These pins are used for serial data outputs. Read Reset: RSTR The first positive transition of SRCK after RSTR becomes high resets the read address pointers to zero. RSTR setup and hold times are referenced to the rising edge of SRCK. Read Enable: RE The function of RE is to gate of the SRCK clock for incrementing the read pointer. When RE is high before the rising edge of SRCK, the read pointer is incremented. When RE is low, the read pointer is not incremented. RE setup times (tRENS and tRDSS) and RE hold times (tRENH and tRDSH) are referenced to the rising edge of the SRCK clock. The latency for the read operation control by RE is 2. After read reset, RE must remain low for more than 1600 ns (tFRD). After read reset, the read data at address 0 is output after a time tRL from the cycle in which WE is brought high. After read reset, RE should be remained high for 2 cycles after driving RE high first. Output Enable: OE OE is used to enable/disable the outputs. OE high level enables the outputs. The internal read address pointer is always incremented by cycling SRCK regardless of the OE level. Note that OE setup and hold times are referenced to the rising edge of SRCK. The latency for the read operation control by OE is 2. 5/18 Semiconductor MS81V06160 Serial Write Clock: SWCK The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer. Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK. Serial Read Clock: SRCK Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high during a read operation. The SRCK input increments the internal read address pointer when RE is high. The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of SRCK. *There are no output valid time restriction on MS8106160. 6/18 Semiconductor MS81V06160 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Power Supply Voltage Input Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VCC VT IOS PD Topr Tstg Condition Ta = 25C Ta = 25C, VSS Ta = 25C Ta = 25C -- -- Rating * 0.5 to +4.6 * 0.5 to +4.6 50 1 0 to 70 * 55 to +150 Unit V V mA W C C Recommended Operating Conditions Parameter Power Supply voltage Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min. 3.0 2.0 * 0.3 Typ. 3.3 VCC 0 Max. 3.6 VCC + 0.2 0.8 Unit V V V DC Characteristics Parameter Input Leakage Current Output Leakage Current Output "H" Level Voltage Output "L" Level Voltage Operating Current Standby Current Symbol ILI ILO VOH VOL ICC1 ICC2 Condition 0 < VI < VCC, Other Pins Tested at V = 0 V 0 < VO < VCC IOH = -2 mA IOH = 2 mA Minimum Cycle Time Output Open Input Pin = VIH/VIL -12 -15 -12 -15 Min. -10 -10 2.4 -- -- -- -- -- Max. +10 +10 -- 0.4 210 170 6 6 Unit V V mA mA Capacitance (VCC = 3.3 V 0.3 V, Ta = 25C, f = 1 MHz) Parameter Input Capacitance Output Capacitance Symbol CI CO Max. 5 7 Unit pF pF 7/18 Semiconductor MS81V06160 AC Characteristics (VCC = 3.3 V 10%, Ta = 0 to 70C) Parameter Access Time from SRCK DOUT Hold Time from SRCK DOUT Enable Time from SRCK SWCK "H" Pulse Width SWCK "L" Pulse Width Input Data Setup Time Input Data Hold Time WE Enable Setup Time WE Enable Hold Time WE Disable Setup Time WE Disable Hold Time IE Enable Setup Time IE Enable Hold Time IE Disable Setup Time IE Disable Hold Time WE "H" Pulse Width WE "L" Pulse Width IE "H" Pulse Width IE "L" Pulse Width RSTW Setup Time RSTW Hold Time SRCK "H" Pulse Width SRCK "L" Pulse Width RE Enable Setup Time RE Enable Hold Time RE Disable Setup Time RE Disable Hold Time OE Enable Setup Time OE Enable Hold Time OE Disable Setup Time OE Disable Hold Time RE "H" Pulse Width RE "L" Pulse Width OE "H" Pulse Width OE "L" Pulse Width RSTR Setup Time RSTR Hold Time SWCK Cycle Time SRCK Cycle Time Transition Time (Rise and Fall) WE "L" Period before W Reset RE "L" Period before R Reset RE Delay after Reset WE Delay after Reset Symbol tAC tDDCK tDECK tWSWH tWSWL tDS tDH tWENS tWENH tWDSS tWDSH tIENS tIENH tIDSS tIDSH tWWEH tWWEL tWIEH tWIEL tRSTWS tRSTWH tWSRH tWSRL tRENS tRENH tRDSS tRDSH tOENS tOENH tODSS tODSH tWREH tWREL tWOEH tWOEL tRSTRS tRSTRH tSWC tSRC tT tLWE tLRE tFRD tFWD MS81V06160-12 Min. -- 3 3 4 4 3 1 3 1 3 1 3 1 3 1 4 4 4 4 3 1 4 4 3 1 3 1 3 1 3 1 4 4 4 4 3 1 12 12 1 3 3 1,600 1,600 Max. 9 -- 9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5 -- -- -- -- MS81V06160-15 Min. -- 3 3 6 6 3 1.5 3 1.5 3 1.5 3 1.5 3 1.5 6 6 6 6 3 1.5 6 6 3 1.5 3 1.5 3 1.5 3 1.5 6 6 6 6 3 1.5 15 15 1 3 3 1,600 1,600 Max. 12 -- 12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns clk clk ns ns 8/18 Semiconductor MS81V06160 Parameter Write Latency Read Latency WE Write Control Latency IE Write Control Latency RE Read Control Latency OE Read Control Latency Symbol tWL tRL tWEL tIEL tREL tOEL MS81V06160-12, MS81V06160-15 4 4 2 2 2 2 Unit clk clk clk clk clk clk AC Characteristic Measuring Conditions Output Compare Level Output Load Input Signal Level Input Signal Rise/Fall Time Input Signal Measuring Reference Level 1.4 V 1 TTL + 30 pF 3.0 V/0.0 V 1 ns 1.4 V Note: Input voltage levels for the AC characteristic measurement are VIH = 3.0 V and VIL = 0 V. When transition time tT becomes 1 ns or more, the input signal reference levels for the parameter measurement are VIH (min.) and VIL (max.). 9/18 Semiconductor MS81V06160 OPERATION MODE Write Operation Cycle The write operation is controlled by four control signals, SWCK, RSTW, WE, and IE. The write operation is accomplished by cycling SWCK, and holding WE high after the write address pointer reset operation or RSTW. RSTW must be performed for internal circuit initialization before write operation. WE must be low before and after the reset cycle (tLWE + tFWD). Each write operation, which begins after RSTW must contain at least 231 active write cycles, i.e., SWCK cycles while WE and IE are high. Settings of WE and IE to the operation mode of Write address pointer and Data input. WE H H L IE H L X Internal Write address pointer Incremented Halted Data input (Latency 2) Input Not input X indicates "don't care" Read Operation Cycle The read operation is controlled by four control signals, SRCK, RSTR, RE, and OE. The read operation is accomplished by cycling SRCK, and holding both RE and OE high after the read address pointer reset operation or RSTR. Each read operation, which begins after RSTR, must contain at least 231 active read cycles, i.e., SRCK cycles while RE and OE are high. RE must be low before and after the reset cycle (tLRE + tFWD). Settings of RE and OE to the operation mode of read address pointer and Data output. RE H H L L OE H L H L Internal Read address pointer Incremented Halted Data output (Latency 2) Output High impedance Output High impedance Power-up and Initialization On power-up, the device is designed to begin proper operation after at least 200 s after Vcc has stabilized to a value within the range of recommended operating conditions. After this 200 s stabilization interval, the following initialization sequence must be performed. Because the read and write address pointers are undefined after power-up, a minimum of 330 dummy write operations (SWCK cycles) and read operations (SRCK cycles) must be performed, followed by an RSTW operation and an RSTR operation, to properly initialize the write and the read address pointer. 10/18 Semiconductor MS81V06160 Old/New Data Access There must be a minimum delay of 600 SWCK cycles between writing into memory and reading out from memory. If reading from the first field starts with an RSTR operation, before the start of writing the second field (before the next RSTW operation), then the data just written will be read out. The start of reading out the first field of data may be delayed past the beginning of writing in the second field of data for as many as 70 SWCK cycles. If the RSTR operation for the first field read-out occurs less than 70 SWCK cycles after the RSTW operation for the second field write-in, then the internal buffering of the device assures that the first field will still be read out. The first field of data that is read out while the second field of data is written is called "old data". In order to read out "new data", i.e., the second field written in, read reset must be input after write address 200 the delay between an RSTW operation and an RSTR operation must be at least 600 SRCK cycles. If the delay between RSTW and RSTR operations is more than 71 but less than 600 cycles, then the data read out will be undetermined. It may be "old data" or "new" data, or a combination of old and new data. Such a timing should be avoided. When the read address delay is between more than 71 and less than 599 or more than 401,408, read data will be undetermined. However, normal write is achieved in this address codition. 11/18 Semiconductor MS81V06160 TIMING DIAGRAM Write Cycle Timing (Write Reset) tWSWH tSWC 0 cycle SWCK tRSTWS tWSWL tRSTWH RSTW tDS tDH DI 0-15 tWL Dn-1 Dn tFWD D0 D1 tLWE WE IE *After write reset, WE should be remained high for 2 cycles after driving WE high first. Write Cycle Timing (Write Enable) 1 cycle 2 cycle 3cycle 4 cycle 5 cycle 6 cycle SWCK tWWEL tWWEH WE tWENH tWDSH tWDSS D3 tWENS DI 0-15 D0 D1 D2 D4 D5 D6 D7 tWEL RSTW L IE H 12/18 Semiconductor MS81V06160 Write Cycle Timing (Input Enable) 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cycle SWCK tWIEL tWIEH IE tIENH tIDSH tIDSS tIENS DI 0-15 D0 D1 D2 tIEL D3 D8 D9 D10 D11 RSTW L H WE 13/18 Semiconductor MS81V06160 Read Cycle Timing (Read Reset) tWSRH tSRC 0 cycle 1 cycle SRCK tRSTRS tWSRL tRSTRH tRL RSTR tFRD tAC DO 0-15 Qn-1 Qn Q0 Q1 tLRE RE H OE *After write reset, RE should be remained high for 2 cycles after driving RE high first. Read Cycle Timing (Read Enable) 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle SRCK tWREL tWREH RE tRENH tRDSH tRDSS tRENS tAC DO 0-15 Q0 Q1 Q2 tREL Q3 Q4 Q5 Q6 Q7 RSTR L H OE 14/18 Semiconductor MS81V06160 Read Cycle Timing (Output Enable) 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cycle 11 cycle SRCK tWOEH tWOEL OE tOENH tODSH tDDCK DO 0-15 Q0 Q1 Q2 Q3 Q8 Q9 Q10 Q11 tODSS tOENS tAC tOEL tDECK RSTR L H RE 15/18 Read/Write Cycle Timing (New Data Read) Semiconductor MS81V06160 16/18 Read/Write Cycle Timing (Old Data Read) Semiconductor MS81V06160 17/18 Semiconductor MS81V06160 Read/Write Cycle Timing 18/18 |
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